Nano solutions for future supercomputers: resolving the von-Neumann bottleneck

Nano solutions for future supercomputers: resolving the von-Neumann bottleneck

Image: The chip developed by researchers during the project. Credit: Saketh Ram Mamidala

Researchers from Lund University benefitted from MAX IV laboratory to find solutions to the long-standing technological challenge: the von-Neumann bottleneck. After nearly year-long research during the pandemic, they successfully integrated the processor and memory onto a single vertical nanowire in a 3D configuration while showcasing in-memory computing with a minimal footprint.

The von-Neumann bottleneck stems from the separation of memory and computing units. Consequently, this increases power loss and delay as information is transmitted between these units. The science and industry worlds have for long looked a solution to this bottleneck to potentially reduce the energy consumption within computing technology. AI, machine learning, and other advanced technological development demand energy-efficient speed and capacity.

In this project, researchers put the transistor and a tiny memory element on the bottom and top of the nanowire, respectively — the closest they can get while also achieving their optimum function. It has even made it possible for the memory to work without a power supply.

“Research has for many years moved in the direction of having a ‘clean’ III-V/high-k interface by removing III-V native oxides favorable for high transistor performance. On the contrary, to our surprise, we encountered high memory performance by controllably growing a III-V interface oxide. That led us to integrate both functionalities, memory, and computing, on a single nanowire by using the same interface, but a little bit different!” says Saketh Ram Mamidala, a doctoral student and one of the scientists involved in the project.

Marching on with the research

The experiment was conducted during the ongoing pandemic from April 2020 to February 2021. The circumstances hindered researchers’ and engineers’ mobility to discuss and solve problems immediately. Nevertheless, the research group and MAX IV team coordinated successfully to minimize delays and keep the project ongoing despite the pandemic-related issues. The interlayer oxide and its composition that enabled memory performance were identified using the XPS measurements at FlexPES beamline.

When asked about the next step of this project, Mamidala says, “We would like to scale up the work by integrating the device in arrays and explore the possibility of using this technology platform for neuromorphic applications by mimicking the biological brain.”



Mamidala Saketh Ram et al, High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon, Nature Electronics (2021). DOI: 10.1038/s41928-021-00688-5

Nanowire transistor with integrated memory to enable future supercomputers, LTH